1. Field of the Invention
This invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a buried common interconnection structure used in the semiconductor memory device.
2. Description of the Related Art
As a nonvolatile semiconductor memory, a NAND flash memory that electrically performs data program and erase operations is known. The NAND flash memory has a plurality of units each including a memory cell group configured by a plurality of memory cells that are serially connected along a first direction and source-side and drain-side select transistors that are respectively serially connected to both ends of the current path of the memory cell group. The above units are arranged in a second direction perpendicular to the first direction. The diffusion regions of the select transistors (source-side transistors) are connected to a common source line extending in the second direction. As contacts that connect the diffusion regions of the source-side select transistors to the common source line, contacts using a buried interconnection layer are disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-188252 (particularly, FIGS. 41 and 42). Further, the transistors (drain-side transistors) are respectively connected to a plurality of bit lines via bit line contacts.
The buried interconnection layer that connects the source-side select transistors to the common source line is formed in the same step as the formation step of the bit line contacts for simplifying the manufacturing process. Since the buried interconnection layer is formed in a line form extending in the second direction, in the step of forming holes for the bit line contacts in an interlayer insulating layer, etching gas tends to more easily enter in a groove for the buried interconnection layer than holes for the bit line contacts. As a result, the groove for the buried interconnection layer may be formed deeper than the holes for the bit line contacts.
Further, when the buried interconnection layer and bit line contacts are formed by a dual damascene method, the groove for the common source interconnection is formed by etching while the groove for the buried interconnection layer is opened. As a result, the bottom of the buried interconnection layer becomes deeper than that of the diffusion region to thereby increase junction leakage.